Synchronous memories, such as synchronous dynamic random access memory (SRAM), double data rate (DDR) SDRAM, Rambus DRAM, have been a main concern in recent years. Synchronous memories implement operations at higher speed than conventional memories and lead in present memory market.
Typically, memory controllers (e.g., CPU) use a combination of control signals so that the memory recognizes commands. For example, when a chip selection signal or a write enable signal is enabled, the memory recognizes it as a write command to perform a write operation. External control signals transmitted from a memory controller to the memory include a chip selection signal, a write enable signal, a column address strobe signal, a row address strobe signal, a clock enable signal, and the like. Since a command is generated by a combination of these external control signals, generally, these control signals are called a command signal. In addition to the command signals, address signals for assigning memory cells are required to perform a read/write operation.
In a normal read/write operation of an SDRAM, as shown in FIG. 1, a memory is provided with a row address together with an active command (consisting of a combination of external control signals), and then provided with a column address together with a read/write command. A test operation is carried out in the same way as a normal read/write operation. That is, the test operation requires command signals and address signals. Generally, the number of pads for receiving address signals is greater in number than that for receiving command signals.
As described above, the test operation needs all pads that are required in the normal read/write operation, which acts as a test limitation factor. For instance, a tester comprises a predetermined number of channels. For this reason, if the number of pads of a memory under test is large, the number of memories that are tested at the same time is decreased. This limitation can be overcome by reducing the number of pads that are required in the normal read/write operation and the test operation.